Understanding Memory Architecture (RAM)
In computer architecture, Random Access Memory (RAM) acts as the primary workspace for the CPU. Memory is fundamentally organized as a vast grid or array of individual storage units, commonly referred to as Words. The physical and logical size of this memory is defined by the relationship between the address bus and the data bus.
The Address Bus and Address Lines (n)
To access a specific piece of data, the CPU must send a binary address to the memory controller via the Address Bus. The number of distinct physical wires (or bits) dedicated to this address is known as the Address Lines (n).
- If a system has n address lines, it can generate exactly 2n unique binary addresses.
- Consequently, the maximum number of Words the memory can contain is precisely equal to 2n.
- For example, a 32-bit address bus allows for 232 (approx. 4.29 billion) unique memory locations.
Word Size (m)
Once the memory controller locates a specific address, it reads or writes data at that location. The amount of data stored at a single address is the Word Size (m). Depending on the architecture, common word sizes include 8 bits (1 byte), 16 bits, 32 bits, or 64 bits. Data travels between the RAM and the CPU via the Data Bus, which is typically the same width as the word size.
The Core Memory Math Formula
The total capacity of a memory chip or module is the product of how many memory locations exist, multiplied by how much data each location can hold.
- Total Capacity (in bits) = 2n × m
- Conversely, if you know the total capacity and the word size, you can work backwards using logarithms to find the required number of address lines:
Address Lines = log2(Total Bits / m)